8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
FLASH MEMORY
MT28F008B3
MT28F800B3
3V ONLY, DUAL SUPPLY (SMART 3)
FEATURES
• Eleven erase blocks:
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
Eight main memory blocks
• Smart 3 technology (B3):
3.3V ±0.3V VCC
3.3V ±0.3V VPP application programming
5V ±10% VPP application/production programming1
• Compatible with 0.3µm Smart 3 device
• Advanced 0.18µm CMOS floating-gate process
• Address access time: 90ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• TSOP, SOP and FBGA packaging options
• Byte- or word-wide READ and WRITE
(MT28F800B3): 1 Meg x 8/512K x 16
Options
48-Pin TSOP Type I
44-Pin SOP
GENERAL DESCRIPTION
The MT28F008B3 (x8) and MT28F800B3 (x16/x8)
are low-voltage, nonvolatile, electrically block-erasable (flash), programmable memory devices containing 8,388,608 bits organized as 524,288 words (16 bits)
or 1,048,576 bytes (8 bits). Writing and erasing the
device is done with a VPP voltage of either 3.3V or 5V,
while all operations are performed with a 3.3V VCC.
Due to process technology advances, 5V VPP is optimal
for application and production programming. These
devices are fabricated with Micron’s advanced 0.18µm
CMOS floating-gate process.
The MT28F008B3 and MT28F800B3 are organized
into eleven separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure
or overwrite, the devices feature a hardware-protected
boot block. This block may be used to store code
implemented in low-level system recovery. The
remaining blocks vary in density and are written and
erased with no additional security measures.
Refer to Micron’s Web site (www.micron.com/flash)
for the latest data sheet.
Marking
• Timing
90ns access
• Configurations
1 Meg x 8
512K x 16/1 Meg x 8
• Boot Block Starting Word Address
Top (7FFFFh)
Bottom (00000h)
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Extended (-40ºC to +85ºC)
• Packages
MT28F008B3
Plastic 40-pin (standard) TSOP Type I
Plastic 40-pin (lead free) TSOP Type I
MT28F800B3
Plastic 48-pin (standard) TSOP Type I
Plastic 48-pin (lead free) TSOP Type I
Plastic 44-pin (standard) SOP
Plastic 44-pin (lead free) SOP
NOTE:
40-Pin TSOP Type I
-9
MT28F008B3
MT28F800B3
T
B
None
ET
VG
VP
WG
WP
SG2
SP2
1. This generation of devices does not support 12V
VPP production programming; however, 5V VPP
application production programming can be
used with no loss of performance.
2. Contact Factory for availability
Part Number Example:
MT28F800B3WG-9
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
1
©2001 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Figure 1: Pin Assignment (Top View)
48-Pin TSOP Type I
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
VPP
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
44-Pin SOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/(A - 1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
VPP
1
44
RP#
A18
2
43
WE#
A17
3
42
A8
A7
4
41
A9
A6
5
40
A10
A5
6
39
A11
A4
7
38
A12
A3
8
37
A13
A2
9
36
A14
A1
10
35
A15
A0
11
34
A16
CE#
12
33
BYTE#
VSS
13
32
VSS
OE#
14
31
DQ15/(A - 1)
DQ0
15
30
DQ7
DQ8
16
29
DQ14
DQ1
17
28
DQ6
DQ9
18
27
DQ13
DQ2
19
26
DQ5
DQ10
20
25
DQ12
DQ3
21
24
DQ4
DQ11
22
23
VCC
ORDER NUMBER AND PART MARKING
MT28F800B3SG-9 B
MT28F800B3SP-9 B
MT28F800B3SG-9 T
MT28F800B3SP-9 T
MT28F800B3SG-9 BET MT28F800B3SP-9 BET
MT28F800B3SG-9 TET MT28F800B3SP-9 TET
ORDER NUMBER AND PART MARKING
MT28F800B3WG-9 B MT28F800B3WP-9 B
MT28F800B3WG-9 T MT28F800B3WP-9 T
MT28F800B3WG-9 BET MT28F800B3WP-9 BET
MT28F800B3WG-9 TET MT28F800B3WP-9 TET
40-Pin TSOP Type I
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
VPP
WP#
A18
A7
A6
A5
A4
A3
A2
A1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A17
VSS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
ORDER NUMBER AND PART MARKING
MT28F008B3VG-9 B
MT28F008B3VP-9 B
MT28F008B3VG-9 T
MT28F008B3VP-9 T
MT28F008B3VG-9 BET MT28F008B3VP-9 BET
MT28F008B3VG-9 TET MT28F008B3VP-9 TET
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
Figure 2: Functional Block Diagran
BYTE# 2
8
Input
Buffer
7
Input
Buffer
I/O
Control
Logic
16KB Boot Block
Addr.
Buffer/
19 (20)
10
X - Decoder/Block Erase Control
A0–A18/(A19)
Latch
A9
9
(10)
Addr.
Power
(Current)
Control
WP#
Counter
1
96KB Main Block
Input
Buffer
128KB Main Block
128KB Main Block
A-1
128KB Main Block
Input Data
Latch/Mux
128KB Main Block
DQ15/(A - 1) 2
128KB Main Block
16
128KB Main Block
DQ8–DQ14 2
128KB Main Block
Command
State
Execution
Machine
Logic
YDecoder
RP#
VCC
3
VPP
8
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
VPP
Switch/
Pump
Output
Buffer
DQ15
Identification
Register
Output
Buffer
7
8
MUX
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.All rights reserved.
Status
Register
8
NOTE:
1. Does not apply to MT28F800B3SG.
2. Does not apply to MT28F008B3.
DQ0–DQ7
7
Y - Select Gates
Output
Buffer
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
CE#
OE#
WE#
8KB Parameter Block
8KB Parameter Block
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Table 1:
Pin Descriptions
44-PIN
SOP
NUMBERS
40-PIN
TSOP
NUMBERS
48-PIN
TSOP
NUMBERS
SYMBOL
TYPE
DESCRIPTION
43
9
11
WE#
Input
–
12
14
WP#
Input
12
22
26
CE#
Input
44
10
12
RP#
Input
14
24
28
OE#
Input
33
–
47
BYTE#
Input
A0–A18/
(A19)
Input
Write Enable: Determines if a given cycle is a WRITE cycle.
If WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
Write Protect: Unlocks the boot block when HIGH if VPP =
VPPH1 (3.3V) or VPPH2 (5V) and RP# = VIH during a WRITE or
ERASE. Does not affect WRITE or ERASE operation on
other blocks.
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
Reset/Power-Down: When LOW, RP# clears the status
register, sets the internal state machine (ISM) to the array
read mode and places the device in deep power-down
mode. All inputs, including CE#, are “Don’t Care,” and all
outputs are High-Z. RP# unlocks the boot block and
overrides the condition of WP# when at VHH (12V), and
must be held at VIH during all other modes of operation.
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active
through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are HighZ, and all data is accessed through DQ0–DQ7. DQ15/(A-1)
becomes the least significant address input.
Address Inputs: Select a unique 16-bit word or 8-bit byte.
The DQ15/(A-1) input becomes the lowest order address
when BYTE# = LOW (MT28F800B3) to allow for a selection
of an 8-bit byte from the 1,048,576 available.
11, 10, 9, 8,
7, 6, 5, 4,
42, 41, 40,
39, 38, 37,
36, 35, 34,
3, 2
31
21, 20, 19,
25, 24, 23,
18, 17, 16,
22, 21, 20,
15, 14, 8, 7, 19, 18, 8, 7,
36, 6, 5, 4, 6, 5, 4, 3, 2,
3, 2, 1, 40, 1, 48, 17, 16
13, 37
–
45
15, 17, 19,
21, 24, 26,
28, 30
16, 18, 20,
22, 25, 27,
29
1
25, 26, 27,
28, 32, 33,
34, 35
–
11
29, 31, 33,
35, 38, 40,
42, 44
30, 32, 34,
36, 39, 41,
43
13
23
30, 31
37
Vcc
13, 32
–
23, 39
29,38
27, 46
9,10,15
VSS
NC
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
DQ15/
(A-1)
DQ0–
DQ7
DQ8–
DQ14
VPP
Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input:
Output LSB of address input when BYTE# = LOW during READ or
WRITE operation.
Input/ Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE. These pins are used to
input commands to the CEL.
Input/ Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE when BYTE# = HIGH. These
pins are High-Z when BYTE# is LOW.
Supply Write/Erase Supply Voltage: From a WRITE or ERASE
CONFIRM until completion of the WRITE or ERASE, VPP
must be at VPPH1 (3.3V) or VPPH2 (5V). VPP = “Don’t Care”
during all other operations.
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
–
NoConnect:Thesepinsmaybedrivenorleftunconnected.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Table 2:
Truth Table (MT28F800B3)1
FUNCTION
RP#
H
Standby
L
RESET
READ
H
READ (word mode)
H
READ (byte mode)
H
Output Disable
WRITE/ERASE (EXCEPT BOOT BLOCK)2
H
ERASE SETUP
H
ERASE CONFIRM3
H
WRITE SETUP
H
WRITE (word mode)4
H
WRITE (byte mode)4
5
H
READ ARRAY
WRITE/ERASE (BOOT BLOCK)2, 7
H
ERASE SETUP
VHH
ERASE CONFIRM3
H
ERASE CONFIRM3, 6
H
WRITE SETUP
VHH
WRITE (word mode)4
H
WRITE (word mode)4, 6
VHH
WRITE (byte mode)4
H
WRITE (byte mode)4, 6
5
H
READ ARRAY
DEVICE IDENTIFICATION8, 9
Manufacturer Compatibility
(word mode)10
Manufacturer Compatibility
(byte mode)
Device (word mode, top boot)10
Device (byte mode, top boot)
Device (word mode, bottom
boot)10
Device (byte mode, bottom
boot)
CE#
OE# WE# WP#
BYTE#
A0
A9
VPP
DQ0–
DQ7
DQ8–
DQ14
DQ15/
A-1
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
H
H
H
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VPPH
X
VPPH
VPPH
X
20h
D0h
10h/40h
Data-In
Data-In
FFh
X
X
X
Data-In
X
X
X
X
X
Data-In
A-1
X
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
X
X
H
X
X
H
X
H
X
X
X
X
X
H
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VPPH
VPPH
X
VPPH
VPPH
VPPH
v
X
20h
D0h
D0h
10h/40h
Data-In
Data-In
Data-In
Data-In
FFh
X
X
X
X
Data-In
Data-In
X
X
X
X
X
X
X
Data-In
Data-In
A-1
A-1
X
H
L
L
H
X
H
L
VID
X
89h
00h
–
H
L
L
H
X
L
L
VID
X
89h
High-Z
X
H
H
H
L
L
L
L
L
L
H
H
H
X
X
X
H
L
H
H
H
H
VID
VID
VID
X
X
X
9Ch
9Ch
9Dh
88h
High-Z
88h
–
X
–
H
L
L
H
X
L
H
VID
X
9Dh
High-Z
X
Data-Out Data-Out Data-Out
Data-Out
High-Z
A-1
High-Z
High-Z
High-Z
NOTE:
1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).
2. VPPH = VPPH1 = 3.3V or VPPH2 = 5V.
3. Operation must be preceded by ERASE SETUP command.
4. Operation must be preceded by WRITE SETUP command.
5. The READ ARRAY command must be issued before reading the array after writing or erasing.
6. When WP# = VIH, RP# may be at VIH or VHH.
7. VHH = 12V.
8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.
9. A1–A8, A10–A18 = VIL.
10. Value reflects DQ8–DQ15.
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Table 3:
Truth Table (MT28F008B3)1
FUNCTION
RP#
H
Standby
L
RESET
READ
H
READ
H
Output Disable
WRITE/ERASE (EXCEPT BOOT BLOCK)2
H
ERASE SETUP
H
ERASE CONFIRM3
H
WRITE SETUP
H
WRITE4
H
READ ARRAY5
2, 7
WRITE/ERASE (BOOT BLOCK)
H
ERASE SETUP
VHH
ERASE CONFIRM3
H
ERASE CONFIRM3, 6
H
WRITE SETUP
VHH
WRITE4
H
WRITE4, 6
5
H
READ ARRAY
DEVICE IDENTIFICATION8, 9
H
Manufacturer Compatibility
H
Device (top boot)
H
Device (bottom boot)
CE#
OE#
WE#
WP#
A0
A9
VPP
DQ0–DQ7
H
X
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
High-Z
L
L
L
H
H
H
X
X
X
X
X
X
X
X
Data-Out
High-Z
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VPPH
X
VPPH
X
20h
D0h
10h/40h
Data-In
FFh
L
L
L
L
L
L
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
X
X
H
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VPPH
VPPH
X
VPPH
VPPH
X
20h
D0h
D0h
10h/40h
Data-In
Data-In
FFh
L
L
L
L
L
L
H
H
H
X
X
X
L
H
H
VID
VID
VID
X
X
X
89h
98h
99h
NOTE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
L = VIL, H = VIH, X = VIL or VIH.
VPPH = VPPH1 = 3.3V or VPPH2 = 5V.
Operation must be preceded by ERASE SETUP command.
Operation must be preceded by WRITE SETUP command.
The READ ARRAY command must be issued before reading the array after writing or erasing.
When WP# = VIH, RP# may be at VIH or VHH.
VHH = 12V.
VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.
A1–A8, A10–A19 = VIL.
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Functional Description
The MT28F800B3 and MT28F008B3 Flash devices
incorporate a number of features ideally suited for system firmware. The memory array is segmented into
individual erase blocks. Each block may be erased
without affecting data stored in other blocks. These
memory blocks are read, written and erased with commands to the command execution logic (CEL). The
CEL controls the operation of the internal state
machine (ISM), which completely controls all WRITE,
BLOCK ERASE and VERIFY operations. The ISM protects each memory location from over-erasure and
optimizes each memory location for maximum data
retention. In addition, the ISM greatly simplifies the
control necessary for writing the device insystem or in
an external programmer.
The Functional Description provides detailed information on the operation of the MT28F800B3 and
MT28F008B3 and is organized into these sections:
• Overview
• Memory Architecture
• Output (READ) Operations
• Input Operations
• Command Set
• ISM Status Register
• Command Execution
• Error Handling
• WRITE/ERASE Cycle Endurance
• Power Usage
• Power-Up
(3.3V or 5V) on the VPP pin before a WRITE or ERASE is
performed on the boot block. The remaining blocks
require that only the VPP voltage be present on the VPP
pin before writing or erasing.
Overview
Internal State Machine (ISM)
Hardware-Protected Boot block
This block of the memory array can be erased or
written only when the RP# pin is taken to VHH or when
the WP# pin is brought HIGH. (The WP# pin does not
apply to the SOP package.) This provides additional
security for the core firmware during in-system firmware updates should an unintentional power fluctuation or system reset occur. The MT28F800B3 and
MT28F008B3 are available with the boot block starting
at the bottom of the address space (“B” suffix) and the
top of the address space (“T” suffix).
Selectable Bus Size (MT28F800B3)
The MT28F800B3 allows selection of an 8-bit (1 Meg
x 8) or 16-bit (512K x 16) data bus for reading and writing the memory. The BYTE# pin is used to select the
bus width. In the x16 configuration, control data is
read or written only on the lower eight bits (DQ0–
DQ7).
Data written to the memory array utilizes all active
data pins for the selected configuration. When the x8
configuration is selected, data is written in byte form;
when the x16 configuration is selected, data is written
in word form.
BLOCK ERASE and BYTE/WORD WRITE timing are
simplified with an ISM that controls all erase and write
algorithms in the memory array. The ISM ensures protection against overerasure and optimizes write margin to each cell.
During WRITE operations, the ISM automatically
increments and monitors WRITE attempts, verifies
write margin on each memory cell and updates the
ISM status register. When BLOCK ERASE is performed,
the ISM automatically overwrites the entire addressed
block (eliminates overerasure), increments and monitors ERASE attempts, and sets bits in the ISM status
register.
Smart 3 Technology (B3)
Smart 3 operation allows maximum flexibility for
insystem READ, WRITE and ERASE operations. WRITE
and ERASE operations may be executed with a VPP
voltage of 3.3V or 5V. Due to process technology
advances, 5V VPP is optimal for application and production programming.
Eleven Indeoendently Erasable Memory
Blocks
The MT28F800B3 and MT28F008B3 are organized
into eleven independently erasable memory blocks
that allow portions of the memory to be erased without affecting the rest of the memory data. A special
boot block is hardware-protected against inadvertent
erasure or writing by requiring either a super-voltage
on the RP# pin or driving the WP# pin HIGH. (The WP#
pin does not apply to the SOP package.) One of these
two conditions must exist along with the VPP voltage
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
ISM Status Register
The ISM status register enables an external processor to monitor the status of the ISM during WRITE and
ERASE operations. Two bits of the 8-bit status register
are set and cleared entirely by the ISM. These bits indicate whether the ISM is busy with an ERASE or WRITE
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
ERASE function is block-oriented. All READ and
WRITE operations are done on a random-access basis.
The boot block is protected from unintentional
ERASE or WRITE with a hardware protection circuit
which requires that a super-voltage be applied to RP#
or that the WP# pin be driven HIGH before erasure is
commenced. The boot block is intended for the core
firmware required for basic system functionality. The
remaining ten blocks do not require that either of
these two conditions be met before WRITE or ERASE
operations.
task and when an ERASE has been suspended. Additional error information is set in three other bits: VPP
status, write status and erase status.
Command Execution Logic (CEL)
The CEL receives and interprets commands to the
device. These commands control the operation of the
ISM and the read path (i.e., memory array, ID register
or status register). Commands may be issued to the
CEL while the ISM is active. However, there are restrictions on what commands are allowed in this condition.
See the Command Execution section for more detail.
Boot Block
Deep Power-Down Mode
The hardware-protected boot block provides extra
security for the most sensitive portions of the firmware. This 16KB block may only be erased or written
when the RP# pin is at the specified boot block unlock
voltage (VHH) of 12V or when the WP# pin is HIGH.
During a WRITE or ERASE of the boot block, the RP#
pin must be held at VHH or the WP# pin held HIGH
until the WRITE or ERASE is completed. (The WP# pin
does not apply to the SOP package.) The VPP pin must
be at VPPH (3.3V or 5V) when the boot block is written
to or erased.
The MT28F800B3 and MT28F008B3 are available
in two configurations and top or bottom boot block.
The top boot block version supports processors of the
x86 variety. The bottom boot block version is
intended for 680X0 and RISC applications. Figure 3
illustrates the memory address maps associated with
these two versions.
To allow for maximum power conservation, the
MT28F800B3 and MT28F008B3 feature a very low
current, deep power-down mode. To enter this mode,
the RP# pin is taken to VSS ±0.2V. In this mode, the current draw is a maximum of 8µA at 3.3V VCC. Entering
deep power-down also clears the status register and
sets the ISM to the read array mode.
Memory Architecture
The MT28F800B3 and MT28F008B3 memory array
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into eleven addressable blocks that vary in size
and are independently erasable. When blocks rather
than the entire array are erased, total device endurance is enhanced, as is system flexibility. Only the
Figure 3: Memory Address Maps
BYTE ADDRESS
WORD ADDRESS
BYTE ADDRESS
WORD ADDRESS
7FFFFh
FFFFFh
7FFFFh
FFFFFh
7E000h
7DFFFh
7D000h
7CFFFh
7C000h
7BFFFh
FC000h
FBFFFh
FA000h
F9FFFh
F8000h
F7FFFh
70000h
6FFFFh
E0000h
DFFFFh
60000h
5FFFFh
C0000h
BFFFFh
50000h
4FFFFh
A0000h
9FFFFh
40000h
3FFFFh
80000h
7FFFFh
30000h
2FFFFh
60000h
5FFFFh
20000h
1FFFFh
40000h
3FFFFh
10000h
0FFFFh
20000h
1FFFFh
00000h
00000h
16KB Boot Block
128KB Main Block
70000h
6FFFFh
E0000h
DFFFFh
60000h
5FFFFh
C0000h
BFFFFh
50000h
4FFFFh
A0000h
9FFFFh
40000h
3FFFFh
80000h
7FFFFh
30000h
2FFFFh
60000h
5FFFFh
20000h
1FFFFh
40000h
3FFFFh
10000h
0FFFFh
20000h
1FFFFh
04000h
03FFFh
03000h
02FFFh
02000h
01FFFh
08000h
07FFFh
06000h
05FFFh
04000h
03FFFh
00000h
00000h
128KB Main Block
8KB Parameter Block
96KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
8KB Parameter Block
128KB Main Block
8KB Parameter Block
128KB Main Block
16KB Boot Block
Bottom Boot
MT28F008B3/800B3xx-xxB
09005aef81136a91
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8KB Parameter Block
Top Boot
MT28F008B3/800B3xx-xxT
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©2001 Micron Technology, Inc. All rights reserved.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Parameter Blocks
Status Register
The two 8KB parameter blocks store less sensitive
and more frequently changing system parameters and
also may store configuration or diagnostic coding.
These blocks are enabled for erasure when the VPP pin
is at VPPH. No super-voltage unlock or WP# control is
required.
Performing a READ of the status register requires
the same input sequencing as a READ of the array
except that the address inputs are “Don’t Care.” The
status register contents are always output on DQ0–
DQ7, regardless of the condition of BYTE# on the
MT28F800B3. DQ8–DQ15 are LOW when BYTE# is
HIGH, and DQ8–DQ14 are High-Z when BYTE# is
LOW. Data from the status register is latched on the
falling edge of OE# or CE#, whichever occurs last. If the
contents of the status register change during a READ of
the status register, either OE# or CE# may be toggled
while the other is held LOW to update the output.
Following a WRITE or ERASE, the device automatically enters the status register read mode. In addition,
a READ during a WRITE or ERASE produces the status
register contents on DQ0–DQ7. When the device is in
the erase suspend mode, a READ operation produces
the status register contents until another command is
issued. In certain other modes, READ STATUS REGISTER may be given to return to the status register read
mode. All commands and their operations are
described in the Command Set and Command Execution sections.
Main Memory Blocks
The eight remaining blocks are general-purpose
memory blocks and do not require a super-voltage on
RP# or WP# control to be erased or written. These
blocks are intended for code storage, ROM-resident
applications or operating systems that require in-system update capability.
Output (READ) Operations
The MT28F800B3 and MT28F008B3 feature three
different types of READs. Depending on the current
mode of the device, a READ operation produces data
from the memory array, status register or device identification register. In each of these three cases, the
WE#, CE# and OE# inputs are controlled in a similar
manner. Moving between modes to perform a specific
READ is described in the Command Execution section.
Identification Register
A READ of the two 8-bit device identification registers requires the same input sequencing as a READ of
the array. WE# must be HIGH, and OE# and CE# must
be LOW. However, ID register data is output only on
DQ0–DQ7, regardless of the condition of BYTE# on the
MT28F800B3. A0 is used to decode between the two
bytes of the device ID register; all other address inputs
are “Don’t Care.” When A0 is LOW, the manufacturer
compatibility ID is output, and when A0 is HIGH, the
device ID is output. DQ8–DQ15 are High-Z when
BYTE# is LOW. When BYTE# is HIGH, DQ8–DQ15 are
00h when the manufacturer compatibility ID is read
and 88h when the device ID is read.
To get to the identification register read mode,
READ IDENTIFICATION may be issued while the
device is in certain other modes. In addition, the identification register read mode can be reached by applying a super-voltage (VID) to the A9 pin. Using this
method, the ID register can be read while the device is
in any mode. When A9 is returned to VIL or VIH, the
device returns to the previous mode.
Memory Array
To read the memory array, WE# must be HIGH, and
OE# and CE# must be LOW. Valid data is output on the
DQ pins when these conditions have been met, and a
valid address is given. Valid data remains on the DQ
pins until the address changes, or until OE# or CE#
goes HIGH, whichever occurs first. The DQ pins continue to output new data after each address transition
as long as OE# and CE# remain LOW.
The MT28F800B3 features selectable bus widths.
When the memory array is accessed as a 512K x 16,
BYTE# is HIGH, and data is output on DQ0–DQ15. To
access the memory array as a 1 Meg x 8, BYTE# must
be LOW, DQ8–DQ14 must be High-Z, and all data must
be output on DQ0–DQ7. The DQ15/(A-1) pin becomes
the lowest order address input so that 1,048,576 locations can be read.
After power-up or RESET, the device is automatically in the array read mode. All commands and their
operations are covered in the Command Set and Command Execution sections.
09005aef81136a91
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Input Operations
must be HIGH, CE# and WE# must be LOW, and VPP
must be set to VPPH1 or VPPH2. Writing to the boot
block also requires that the RP# pin be at VHH or WP#
be HIGH. A0–A18 (A19) provide the address to be written, while the data to be written to the array is input on
the DQ pins. The data and addresses are latched on the
rising edge of CE# (CE#-controlled) or WE# (WE#-controlled), whichever occurs first. A WRITE must be preceded by a WRITE SETUP command. Details on how to
input data to the array are described in the Write
Sequence section.
Selectable bus sizing applies to WRITEs as it does to
READs on the MT28F800B3. When BYTE# is LOW (byte
mode), data is input on DQ0–DQ7, DQ8–DQ14 are
High-Z, and DQ15 becomes the lowest order address
input. When BYTE# is HIGH (word mode), data is
input on DQ0–DQ15.
The DQ pins are used either to input data to the
array or to input a command to the CEL. A command
input issues an 8-bit command to the CEL to control
the mode of operation of the device. A WRITE is used
to input data to the memory array. The following section describes both types of inputs. More information
describing how to use the two types of inputs to write
or erase the device is provided in the Command Execution section.
Commands
To perform a command input, OE# must be HIGH,
and CE# and WE# must be LOW. Addresses are “Don’t
Care” but must be held stable, except during an ERASE
CONFIRM (described in a later section). The 8-bit
command is input on DQ0–DQ7, while DQ8–DQ15 are
“Don’t Care” on the MT28F800B3. The command is
latched on the rising edge of CE# (CE#-controlled) or
WE# (WE#-controlled), whichever occurs first. The
condition of BYTE# on the MT28F800B3 has no effect
on a command input.
Command Set
To simplify writing of the memory blocks, the
MT28F800B3 and MT28F008B3 incorporate an ISM
that controls all internal algorithms for writing and
erasing the floating gate memory cells. An 8-bit command set is used to control the device. Details on how
to sequence commands are provided in the Command
Execution section. Table 4 lists the valid commands.
Memory Array
A WRITE to the memory array sets the desired bits
to logic 0s but cannot change a given bit to a logic 1
from a logic 0. Setting any bits to a logic 1 requires that
the entire block be erased. To perform a WRITE, OE#
Table 4:
Command Set
COMMAND
HEX CODE
RESERVED
00h
READ ARRAY
FFh
IDENTIFY DEVICE
90h
READ STATUS REGISTER
70h
CLEAR STATUS REGISTER
ERASE SETUP
50h
20h
ERASE CONFIRM/RESUME
D0h
WRITE SETUP
ERASE SUSPEND
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40h or 10h
B0h
DESCRIPTION
This command and all unlisted commands are invalid and should not be
called. These commands are reserved to allow for future feature
enhancements.
Must be issued after any other command cycle before the array can be
read. It is not necessary to issue this command after power-up or RESET.
Allows the device and manufacturer compatibility ID to be read. A0 is used
to decode between the manufacturer compatibility ID (A0 = LOW) and
device ID (A0 = HIGH).
Allows the status register to be read. Please refer to Table 5 for more
information on the status register bits.
Clears status register bits 3-5, which cannot be cleared by the ISM.
The first command given in the two-cycle ERASE sequence. The ERASE is
not completed unless followed by ERASE CONFIRM.
The second command given in the two-cycle ERASE sequence. Must follow
an ERASE SETUP command to be valid. Also used during an ERASE SUSPEND
to resume the ERASE.
The first command given in the two-cycle WRITE sequence. The write data
and address are given in the following cycle to complete the WRITE.
Requests a halt of the ERASE and puts the device into the erase suspend
mode. When the device is in this mode, only READ STATUS REGISTER, READ
ARRAY and ERASE RESUME commands may be executed.
10
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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
ISM Status Register
All of the defined bits are set by the ISM, but only
the ISM and erase suspend status bits are reset by the
ISM. The erase, write and VPP status bits must be
cleared using CLEAR STATUS REGISTER. If the VPP
status bit (SR3) is set, the CEL does not allow further
WRITE or ERASE operations until the status register is
cleared. This enables the user to choose when to poll
and clear the status register. For example, the host system may perform multiple BYTE WRITE operations
before checking the status register instead of checking
after each individual WRITE. Asserting the RP# signal
or powering down the device also clears the status register.
The 8-bit ISM status register (see Table 5) is polled
to check for WRITE or ERASE completion or any
related errors. During or following a WRITE, ERASE or
ERASE SUSPEND, a READ operation outputs the status
register contents on DQ0–DQ7 without prior command. While the status register contents are read, the
outputs are not be updated if there is a change in the
ISM status unless OE# or CE# is toggled. If the device is
not in the write, erase, erase suspend or status register
read mode, READ STATUS REGISTER (70h) can be
issued to view the status register contents.
Table 5:
Status Register Bit Definitions
ISMS
ESS
ES
WS
VPPS
R
7
6
5
4
3
2–0
STATUS BIT #
SR7
SR6
SR5
SR4
SR3
SR0–2
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STATUS REGISTER BIT
ISM STATUS (ISMS)
1 = Ready
0 = Busy
ERASE SUSPEND STATUS (ESS)
1 = ERASE suspended
0 = ERASE in progress/completed
ERASE STATUS (ES)
1 = BLOCK ERASE error
0 = Successful BLOCK ERASE
WRITE STATUS (WS)
1 = WORD/BYTE WRITE error
0 = Successful WORD/BYTE WRITE
VPP STATUS (VPPS)
1 = No VPP voltage detected
0 = VPP present
RESERVED
DESCRIPTION
The ISMS bit displays the active status of the state machine during
WRITE or BLOCK ERASE operations. The controlling logic polls this bit
to determine when the erase and write status bits are valid.
Issuing an ERASE SUSPEND places the ISM in the suspend mode and
sets this and the ISMS bit to “1.” The ESS bit remains “1” until an
ERASE RESUME is issued.
ES is set to “1” after the maximum number of ERASE cycles is
executed by the ISM without a successful verify. ES is only cleared by a
CLEAR STATUS REGISTER command or after a RESET.
WS is set to “1” after the maximum number of WRITE cycles is
executed by the ISM without a successful verify. WS is only cleared by
a CLEAR STATUS REGISTER command or after a RESET.
VPPS detects the presence of a VPP voltage. It does not monitor VPP
continuously, nor does it indicate a valid VPP voltage. The VPP pin is
sampled for 3.3V or 5V after WRITE or ERASE CONFIRM is given. VPPS
must be cleared by CLEAR STATUS REGISTER or by a RESET.
Reserved for future use.
11
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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Command Execution
the write address and data are issued and VPP is
brought to VPPH. Writing to the boot block also
requires that the RP# pin be brought to VHH or the WP#
pin be brought HIGH at the same time VPP is brought
to VPPH. The ISM now begins to write the word or byte.
VPP must be held at VPPH until the WRITE is completed
(SR7 = 1).
While the ISM executes the WRITE, the ISM status
bit (SR7) is at 0, and the device does not respond to any
commands. Any READ operation produces the status
register contents on DQ0–DQ7. When the ISM status
bit (SR7) is set to a logic 1, the WRITE has been completed, and the device goes into the status register read
mode until another command is given.
After the ISM has initiated the WRITE, it cannot be
aborted except by a RESET or by powering down the
part. Doing either during a WRITE corrupts the data
being written. If only the WRITE SETUP command has
been given, the WRITE may be nullified by performing
a null WRITE. To execute a null WRITE, FFh must be
written when BYTE# is LOW, or FFFFh must be written
when BYTE# is HIGH. When the ISM status bit (SR7)
has been set, the device is in the status register read
mode until another command is issued.
Commands are issued to bring the device into different operational modes. Each mode allows specific
operations to be performed. Several modes require a
sequence of commands to be written before they are
reached. The following section describes the properties of each mode, and Table 6 lists all command
sequences required to perform the desired operation.
Read Array
The array read mode is the initial state of the device
upon power-up and after a RESET. If the device is in
any other mode, READ ARRAY (FFh) must be given to
return to the array read mode. Unlike the WRITE
SETUP command (40h), READ ARRAY does not need
to be given before each individual READ access.
IDENTIFY DEVICE
IDENTIFY DEVICE (90h) may be written to the CEL
to enter the identify device mode. While the device is
in this mode, any READ produces the device identification when A0 is HIGH and the manufacturer compatibility identification when A0 is LOW. The device
remains in this mode until another command is given.
Write Sequence
Two consecutive cycles are needed to input data to
the array. WRITE SETUP (40h or 10h) is given in the
first cycle. The next cycle is the WRITE, during which
Table 6:
Command Sequences
COMMANDS
READ ARRAY
IDENTIFY DEVICE
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP/CONFIRM
ERASE SUSPEND/RESUME
WRITE SETUP/WRITE
ALTERNATE WORD/BYTE WRITE
BUS
CYCLES
REQ’D
OPERATION
ADDRESS
FIRST
CYCLE
DATA
1
3
2
1
2
2
2
2
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
X
X
X
X
X
X
X
X
FFh
90h
70h
50h
20h
B0h
40h
10h
OPERATION SECOND
ADDRESS
CYCLE
DATA
NOTES
1
2, 3
4
READ
READ
IA
X
ID
SRD
WRITE
WRITE
WRITE
WRITE
BA
X
WA
WA
D0h
D0h
WD
WD
5, 6
6, 7
6, 7
NOTE:
1.
2.
3.
4.
5.
6.
7.
Must follow WRITE or ERASE CONFIRM commands to the CEL in order to enable Flash array READ cycles.
IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.
ID = Identify Data.
SRD = Status Register Data.
BA = Block Address (A12–A19).
Addresses are “Don’t Care” in first cycle but must be held stable.
WA = Address to be written; WD = Data to be written to WA.
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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
ERASE Sequence
ERASE Suspension
Executing an ERASE sequence sets all bits within a
block to logic 1. The command sequence necessary to
execute an ERASE is similar to that of a WRITE. To provide added security against accidental block erasure,
two consecutive command cycles are required to initiate an ERASE of a block. In the first cycle, addresses
are “Don’t Care,” and ERASE SETUP (20h) is given. In
the second cycle, VPP must be brought to VPPH, an
address within the block to be erased must be issued,
and ERASE CONFIRM (D0h) must be given. If a command other than ERASE CONFIRM is given, the write
and erase status bits (SR4 and SR5) are set, and the
device is in the status register read mode.
After the ERASE CONFIRM (D0h) is issued, the ISM
starts the ERASE of the addressed block. Any READ
operation outputs the status register contents on
DQ0–DQ7. VPP must be held at VPPH until the ERASE is
completed (SR7 = 1). When the ERASE is completed,
the device is in the status register read mode until
another command is issued. Erasing the boot block
also requires that either the RP# pin be set to VHH or
the WP# pin be held HIGH at the same time VPP is set
to VPPH.
The only command that may be issued while an
ERASE is in progress is ERASE SUSPEND. This command enables other commands to be executed while
pausing the ERASE in progress. When the device has
reached the erase suspend mode, the erase suspend
status bit (SR6) and ISM status bit (SR7) are set. The
device may now be given a READ ARRAY, ERASE
RESUME or READ STATUS REGISTER command. After
READ ARRAY has been issued, any location not within
the block being erased may be read. If ERASE RESUME
is issued before SR6 has been set, the device immediately proceeds with the ERASE in progress.
Table 7:
Error Handling
After the ISM status bit (SR7) has been set, the VPP
(SR3), write (SR4) and erase (SR5) status bits may be
checked. If one or a combination of these three bits
has been set, an error has occurred. The ISM cannot
reset these three bits. To clear these bits, CLEAR STATUS REGISTER (50h) must be given. If the VPP status
bit (SR3) is set, further WRITE or ERASE operations
cannot resume until the status register is cleared.
Table 7 lists the combination of errors.
Status Register Error Code Description1
STATUS BITS
SR5
SR4
SR3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ERROR DESCRIPTION
No errors
VPP voltage error
WRITE error
WRITE error, VPP voltage not valid at time of WRITE
ERASE error
ERASE error, VPP voltage not valid at time of ERASE CONFIRM
Command sequencing error or WRITE/ERASE error
Command sequencing error, VPP voltage error, with WRITE and ERASE errors
NOTE:
1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.
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13
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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
WRITE/ERASE Cycle Endurance
Power-Up
The MT28F800B3 and MT28F008B3 are designed
and fabricated to meet advanced firmware storage
requirements. To ensure this level of reliability, VPP
must be at 3.3V ±0.3V or 5V ±10% during WRITE or
ERASE cycles. Due to process technology advances, 5V
VPP is optimal for application and production programming.
The likelihood of unwanted WRITE or ERASE operations is minimized because two consecutive cycles are
required to execute either operation. However, to reset
the ISM and to provide additional protection while VCC
is ramping, one of the following conditions must be
met:
• RP# must be held LOW until VCC is at valid functional level; or
• CE# or WE# may be held HIGH and RP# must be
toggled from VCC-GND-VCC.
After a power-up or RESET, the status register is
reset, and the device enters the array read mode.
Power Usage
The MT28F800B3 and MT28F008B3 offer several
power-saving features that may be utilized in the array
read mode to conserve power. Deep power-down
mode is enabled by bringing RP# LOW. Current draw
(ICC) in this mode is a maximum of 8µA at 3.3V VCC.
When CE# is HIGH, the device enters standby mode. In
this mode, maximum ICC current is 100µA at 3.3V VCC.
If CE# is brought HIGH during a WRITE or ERASE, the
ISM continues to operate, and the device consumes
the respective active power until the WRITE or ERASE
is completed.
Figure 4: Power-Up/Reset Timing
Diagram
RP#
Note 1
VCC
(3.3V)
t
AA
Address
VALID
VALID
Data
t
RWH
UNDEFINED
NOTE:
1. VCC must be within the valid operating range before RP#
goes HIGH.
NOTE:
1. Vcc must be within the valid operating range before
RP# goes HIGH.
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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Figure 5: Self-Timed WRITE Sequence
(Word or Byte WRITE)1
Figure 6: Complete WRITE
Status-Check Sequence
Start (WRITE completed)
Start
SR3 = 0?
WRITE 40h or 10h
NO
VPP Error 4, 5
NO
BYTE/WORD WRITE Error5
YES
SR4 = 0?
VPP = 3.3V or 5V
YES
WRITE Successful
WRITE Word or Byte
Address/Data
STATUS REGISTER
READ
SR7 = 1?
NO
YES
Complete Status2
Check (optional)
WRITE Complete 3
NOTE:
1. Sequence may be repeated for additional BYTE or WORD WRITEs.
2. Complete status check is not required. However, if SR3 = 1, further WRITEs are inhibited until the status register is
cleared.
3. Device will be in status register read mode. To return to the array read mode, the FFh command must be issued.
4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE or
ERASE operations are allowed by the CEL.
5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
09005aef81136a91
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15
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8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Figure 7: Self-Timed BLOCK ERASE
Sequence1
Figure 8: Complete BLOCK ERASE
Status-Check Sequence
Start
Start (ERASE completed)
WRITE 20h
SR3 = 0?
NO
VPP Error 5, 6
YES
Command Sequence Error6
NO
BLOCK ERASE Error6
YES
VPP = 3.3V or 5V
SR4, 5 = 1?
NO
WRITE D0h,
Block Address
SR5 = 0?
YES
ERASE
Busy
STATUS REGISTER
READ
ERASE Successful
NO
NO
SR7 = 1?
Suspend ERASE?
YES
YES
Complete Status 2
Check (optional)
Suspend 4
Sequence
ERASE Resumed
ERASE Complete
3
NOTE:
1. Sequence may be repeated to erase additional blocks.
2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register is
cleared.
3. To return to the array read mode, the FFh command must be issued.
4. Refer to the ERASE SUSPEND flowchart for more information.
5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE or
ERASE operations are allowed by the CEL.
6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Figure 9: ERASE SUSPEND/RESUME SEQUENCE
Start (ERASE in progress)
WRITE B0h
(ERASE SUSPEND)
VPP = 3.3V or 5V
STATUS REGISTER
READ
SR7 = 1?
NO
YES
SR6 = 1?
NO
YES
ERASE Completed
WRITE FFh
(READ ARRAY)
Done
Reading?
NO
YES
WRITE D0h
(ERASE RESUME)
Resume ERASE
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Absolute Maximum Ratings*
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
**VCC, input and I/O pins may transition to -2V for
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